1. Field of the Invention
The present invention relates to a semiconductor device, more particularly to a structure of a MOS type transistor and a manufacturing method of the same.
2. Description of the Related Art
Attempt to increase an operation speed of transistors has been made as micronization of the transistors processes. Recently, MOS transistors have been developed, which have a gate length less than 0.25 microns. Dimensional limitations to pattern the photoresist has been relieved, thereby advancing micronization of the gate length. However, a contact size, a margin between a contact and a gate, and a margin between the contact and an element isolation insulating layer are not so micronized as a reducing ratio of the gate dimension, whereby reduction in areas of source and drain diffusion layers is difficult. As a result, charging/discharging of capacitances in the source and drain diffusion layers much contributes to an operation speed of the transistors, resulting in producing an obstacle to a high speed operation.
For a method to solve such problems, there has been a method to make reduce source and drain diffusion layer capacitances very small by using an SOI substrate such as a silicon SIMOX. However, there is a problem in the SOI substrate such as the silicon SIMOX that the SOI substrate is inferior to an usual bulk substrate because the SOI substrate is high in cost and has a high density of defects. No SOI substrate has mass-produced yet.
For a method to reduce the source and drain diffusion layer capacitances using the usual bulk substrate, a prior art is disclosed in "A High Performance Super Self-Aligned 3V/5V BiCMOS Technology with Extremely Low Parasitic for Low-Power Mixed-Signal Applications" J. M. Sung et al., IEEE Transaction Electron Devices, Vol. 42, No. 3, 1993, as described below.
First, as shown in FIG. 10(a), a well region 102 is formed on a silicon substrate 101 and an element isolation insulating layer 103 is formed on the silicon substrate 101. Thereafter, a gate oxide film 104 and a gate electrode 105 made of a polysilicon layer is formed sequentially. It should be noted that a nitride film 106 and a polysilicon 105' are stacked on the gate electrode 105. Thereafter, a lightly doped drain ( LDD ) region 107 is formed by injecting impurities into the silicon substrate 105 at a low concentration. Subsequently, as shown in FIG. 10(b), a side wall 108 is formed on a side surface of the gate electrode 105, 106, and 105'. A second polysilicon layer 109 is formed on the entire surface of the resultant structure. The second polysilicon layer 109 is formed so as to contact of a silicon surface of a source and drain formation region.
Next, as shown in FIG. 10(c), the second polysilicon film 109 is subjected to photoresist and etching processes, whereby the film 109 is patterned. Subsequently, as shown in FIG. 10(d), a first photoresist 110 is coated on the entire surface of the resultant structure, whereby the resultant structure is flattened. Furthermore, after a second photoresist 111 is coated on the entire surface of the resultant structure, a portion of the second photoresist 111 located above the gate electrode 105 is removed to form a opening.
Subsequently, as shown in FIG. 10(e), an anisotropic etching is performed so that a thinner portion of the first photoresist 110 is removed. Hence, the second polysilicon 109 is etched. At this time, a portion of the second polysilicon 109 located outside the side wall 108 is sufficiently removed to be over-etched. As a result, the polysilicon 105' on the gate electrode 105 made of the polysilicon is also etched using the nitride film 106 as an etching stopper. Hence, the second polysilicon 109 connecting the source and the drain is divided to two parts interposing the gate electrode 105, each being separated from one another. Thereafter, the nitride film 106 is removed, and an ion injection is performed to form source and drain regions. Then, a thermal treatment for an activation is performed whereby the source and drain regions 112 are formed. Thus, contacts for the source and drain regions 112 are realized through each portion of the second polysilicons 109, respectively, whereby each area of diffusion layers of the source and the drain regions 112 can be made smaller and each diffusion capacitance of them can be reduced greatly.
There has been the problem in the conventional technology that manufacturing processes are very complicated, although the conventional technology can extremely reduce the areas of the diffusion layers of the source and the drain regions. Particularly, two photolithography processes are needed to form the polysilicon electrodes 109 for contacting the source and the drain regions 112 to the outside, and a flattening process using a photoresist is needed. Moreover, as to a structure of this transistor, the side wall 108 displaying a projection shape is left. When a resistor element and alminium wiring, and the like are formed on this transistor, there is a problem that cutting-off of a circuit is caused due to a deterioration of step coverage contributed owing to the projection of the side wall 108.